[dvanblerkom]

TL;DR: ABC_LIBERTY_ARGS passes extra arguments to ABC's read_lib through Yosys's abc -liberty_args (YosysHQ/yosys#5721). Without -S/-G, the mapping library ABC builds from the liberty files gives every cell a delay of 1.0, so the speed script maps for gate count rather than delay. With ABC_LIBERTY_ARGS="-a -G 250", ABC derives a delay for each cell from the liberty tables. Designs that don't set the variable synthesize exactly as before.

• It is applied only to the classic abc call. abc_new (SYNTH_WRAPPED_OPERATORS, SWAP_ARITH_OPERATORS) has no -liberty_args, so it is not added to the shared abc_args.
• The unit delay is visible in ABC: read_lib -w <lib>; write_genlib x.genlib writes PIN * UNKNOWN 1 999 1.00 0.00 1.00 0.00 for every gate. After read_lib -a -G 250 each pin carries its own delay.
• abc: new option to pass extra ABC read_lib args YosysHQ/yosys#5721 measured a 12.0% delay improvement for 4.6% area with -G 250 on 12 designs (NanGate45, post-synthesis STA).
• variables.json and FlowVariables.md are regenerated.

Results

Setup WNS / TNS in ns at CTS, cts__design__instance__area relative to master. One run per configuration.

design	master	ABC_LIBERTY_ARGS="-a -G 250"
sky130hd/jpeg	-0.516 / -71.0	-0.214 / -20.5 (+1.2% area)
sky130hd/riscv32i	-0.634 / -49.2	-0.154 / -0.86 (+0.8%)
nangate45/picorv32	-0.304 / -34.5	-0.238 / -25.8 (+1.1%)
nangate45/ibex	+0.000 / 0	+0.059 / 0 (+3.1%)
nangate45/jpeg (ABC_AREA=1)	-0.106 / -40.3	identical netlist
nangate45/gcd (ABC_AREA=1)	-0.157 / -7.0	identical netlist

abc_area.script (map -B 0.9) produces the same netlist either way.

How this was tested

make synth used this branch's flow/scripts on master cca3a71, with Yosys 0.68+ from the openroad/orfs:26Q4-102-gef421749a image. Floorplan to CTS ran in that image's ORFS on the resulting netlist (SYNTH_NETLIST_FILES). Master's later stages need a newer OpenROAD than that image has. The stages after synthesis are the same for both columns.

Not done: asap7, gf180, ihp-sg13g2, and the CI metrics rules (no design sets the variable, so nothing changes there).

Possible follow-up, not in this PR: make -a -G 250 the default for the speed script. That would change the QoR of every design using the classic abc path, so it needs a CI-wide run first.

🤖 Generated with Claude Code

[gemini-code-assist]

Code Review

This pull request introduces a new configuration variable, ABC_LIBERTY_ARGS, which allows passing extra arguments to ABC's read_lib via Yosys's abc -liberty_args during synthesis. The changes include updating the synthesis script (synth.tcl), documenting the variable in FlowVariables.md, and defining it in both variables.json and variables.yaml. The review feedback recommends replacing the British spelling 'minimises' with the American spelling 'minimizes' in the variable's description across the documentation and configuration files to maintain consistency with the rest of the codebase.

[gemini-code-assist]

To maintain consistency with the rest of the codebase and documentation, please use the American English spelling "minimizes" instead of "minimises".

Suggested change

| <a name="ABC_LIBERTY_ARGS"></a>ABC_LIBERTY_ARGS| Extra arguments for ABC's read_lib, passed with Yosys's abc -liberty_args. Without -S/-G, ABC's mapping library gives every cell a delay of 1, so mapping minimises gate count, not delay. "-a -G 250" derives a delay for each cell from the liberty tables (all cells, gain 250). Ignored when SYNTH_WRAPPED_OPERATORS or SWAP_ARITH_OPERATORS is set: abc_new has no such option.| |

| <a name="ABC_LIBERTY_ARGS"></a>ABC_LIBERTY_ARGS| Extra arguments for ABC's read_lib, passed with Yosys's abc -liberty_args. Without -S/-G, ABC's mapping library gives every cell a delay of 1, so mapping minimizes gate count, not delay. "-a -G 250" derives a delay for each cell from the liberty tables (all cells, gain 250). Ignored when SYNTH_WRAPPED_OPERATORS or SWAP_ARITH_OPERATORS is set: abc_new has no such option.| |

[gemini-code-assist]

To maintain consistency with the rest of the codebase and documentation, please use the American English spelling "minimizes" instead of "minimises".

Suggested change

	"description": "Extra arguments for ABC's read_lib, passed with Yosys's\nabc -liberty_args. Without -S/-G, ABC's mapping library gives every\ncell a delay of 1, so mapping minimises gate count, not delay.\n\"-a -G 250\" derives a delay for each cell from the liberty tables\n(all cells, gain 250). Ignored when SYNTH_WRAPPED_OPERATORS or\nSWAP_ARITH_OPERATORS is set: abc_new has no such option.\n",
	"description": "Extra arguments for ABC's read_lib, passed with Yosys's\nabc -liberty_args. Without -S/-G, ABC's mapping library gives every\ncell a delay of 1, so mapping minimizes gate count, not delay.\n\"-a -G 250\" derives a delay for each cell from the liberty tables\n(all cells, gain 250). Ignored when SYNTH_WRAPPED_OPERATORS or\nSWAP_ARITH_OPERATORS is set: abc_new has no such option.\n",

[gemini-code-assist]

To maintain consistency with the rest of the codebase and documentation, please use the American English spelling "minimizes" instead of "minimises".

    cell a delay of 1, so mapping minimizes gate count, not delay.