[oharboe]

A SYNTH_KEEP_MODULES name that matches no module of the design now stops synthesis, naming it. Before, it was a yosys warning, and synthesis went on with that module flattened.

This is how the keep list in the coralnpu work in progress (#4653) went stale unnoticed. The current RTL renamed DispatchV1, LsuV1 and DBus2AxiV1 to DispatchV2, LsuV3 and DBus2AxiV2, and a full flow ran with three of its ten kept units flattened, its timing results wrong, before anything showed it.

Each name must select a module by one of the two patterns the code already uses: the name itself, or slang's uniquified name$.... The SYNTH_KEEP_MODULES entry in variables.yaml says so.

Checked with ORFS's make:

• asap7/riscv32i, SYNTH_KEEP_MODULES=datapth: stops with SYNTH_KEEP_MODULES: no module datapth in the design.
• asap7/riscv32i, SYNTH_KEEP_MODULES=datapath: passes.
• asap7/chi_async_bridge, whose kept modules have slang's uniquified names: passes unchanged.
• Every name in the three designs that set SYNTH_KEEP_MODULES (chi_async_bridge, swerv_wrapper, and coralnpu in [DO NOT REVIEW] asap7/coralnpu: current RTL from source, SRAMs and register files generated #4653) is a module of its design.

🤖 Generated with Claude Code

[gemini-code-assist]

Code Review

This pull request updates the synthesis script (synth.tcl) to throw an error if a module specified in SYNTH_KEEP_MODULES does not match any module in the design, preventing silent failures due to typos or renamed modules. It also updates the corresponding documentation in FlowVariables.md, variables.json, and variables.yaml to reflect this new behavior. There are no review comments to address, and the changes look solid and well-documented.