All pull requests

Pull requests

• Verilog: constrain assigned slices of arrays in the initial state

  #2321·tautschnig opened Oct 29, 2026Collaborator·

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  1

• KNOWNBUG tests for $typename of associative arrays and unions

  #2320·tautschnig opened Oct 29, 2026Collaborator·

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  3

• Verilog: linear growth for loops over arrays of structs

  #2319·yvizel opened Oct 29, 2026Collaborator·

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  13

• Netlist: auxiliary symbols of the flattening

  #2315·tautschnig opened Oct 29, 2026Collaborator·

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  1

• Verilog: indexed part-selects of packed arrays

  #2314·tautschnig opened Oct 29, 2026Collaborator·

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  1

• Word-level BMC: non-deterministic values in every time frame

  #2313·tautschnig opened Oct 29, 2026Collaborator·

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  2

• Verilog: type of dynamic arrays

  #2301·tautschnig opened Oct 27, 2026Collaborator·3/3·

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  5

• Verilog: RTL construction with system functions of type integer

  #2300·tautschnig opened Oct 27, 2026Collaborator·2/3·

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  1

• Verilog: parameter ports without value

  #2298·tautschnig opened Oct 27, 2026Collaborator·1/3·

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  1

• Verilog preprocessor: `" in macro text

  #2297·tautschnig opened Oct 27, 2026Collaborator·2/2·

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  2

• Verilog: line continuations in string literals

  #2296·tautschnig opened Oct 27, 2026Collaborator·1/2·

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  3

• Verilog: constrain assigned slices of arrays in the initial state

  #2289·tautschnig opened Oct 27, 2026Collaborator·

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  2

• Verilog: out-of-range part-selects on packed arrays

  #2282·tautschnig opened Oct 27, 2026Collaborator·

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  1

• Verilog: liveness-based driver check, dual write ports, free undriven net bits

  Verilog
  #2266·kroening opened Oct 13, 2026Collaborator·

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  1

• Verilog: reject continuous assignment to variables in Verilog and variables on inout ports

  Verilog
  #2265·kroening opened Oct 13, 2026Collaborator·

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  2

• Verilog: local declarations vs. wildcard imports, package variable initializers

  Verilog
  #2262·kroening opened Oct 13, 2026Collaborator·

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  1

• Verilog: while/repeat, always_latch, latch inference in RTL construction

  Verilog
  #2254·kroening opened Oct 13, 2026Collaborator·

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  1

• Verilog: name complex expressions that are read back in RTL construction

  Verilog
  #2216·kroening opened Oct 5, 2026Collaborator·

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  1

  2

• PROTOTYPE: resolve module-instance hierarchical identifiers in the type checker

  Verilog
  #2192·kroening opened Sep 28, 2026Collaborator·

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• Verilog: interface port members are aliases of the bound instance's members

  Verilog
  #2190·tautschnig opened Sep 28, 2026Collaborator·4/4·

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  1

• Verilog: interface ports take the parameters of the bound instance

  Verilog
  #2186·tautschnig opened Sep 28, 2026Collaborator·3/4·

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  6

• remove verilog_synthesis module

  cleanupVerilog
  #2177·kroening opened Sep 27, 2026Collaborator·

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• Verilog: regression test for genvar-indexed instance port connections

  Verilog
  #2163·kroening opened Sep 25, 2026Collaborator·

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• Verilog: upward name referencing

  Verilog
  #2129·kroening opened Sep 14, 2026Collaborator·5 tasks done·

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  1

  2

• Verilog: import of tasks/functions in interfaces and modports

  Verilog
  #2115·kroening opened Aug 21, 2026Collaborator·

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