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H7: keep PLL2 input within the wide VCO's 2-16 MHz range (SD card / FDCAN clock) - #12185
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SYNERDUINOH7 and SYNERDUINOH7A (HSE_MHZ 25) fail to build: the PLL2 block asserts HSE_VALUE is a multiple of 1.6 MHz. For a 25 MHz HSE, use M=10 (VCI 2.5 MHz, inside the 2-16 MHz input range the wide VCO requires per DS12110 Table 50) and scale N so both PLLs keep their existing VCO frequencies: - PLL2: N=320, VCO 800 MHz, VCI range 2-4 MHz - PLL1: N scaled by 4/5 (320/384), VCO 800/960 MHz as with 8/16 MHz HSE Previously PLL1 used M=12 for 25 MHz, giving 417 MHz (rev Y) and an out-of-spec 1000 MHz VCO / 500 MHz core (rev V). Builds for 8 and 16 MHz HSE targets are unchanged.
PLL2 (SDMMC and FDCAN kernel clock) ran with a 1.6 MHz input (8 MHz HSE / 5) on the wide VCO, which DS12110 Tables 50 and 147 specify for 2-16 MHz input only. The medium VCO accepts 1-2 MHz but tops out at 420 MHz, so the 800 MHz VCO was out of spec either way. Use a 4 MHz input for 8/16 MHz HSE (M=2/4, N=200) and 5 MHz for 25 MHz HSE (M=5, N=160), with VCIRANGE_2 (4-8 MHz). The VCO stays at 800 MHz, so the P/Q/R outputs (400/80/200 MHz) are unchanged.
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PR Summary by QodoKeep STM32H7 PLL2 input within the wide-VCO range
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Test firmware build ready — commit Download firmware for PR #12185 251 targets built. Find your board's
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Summary
PLL2 drives the kernel clocks for SDMMC (SD card blackbox) and FDCAN (DroneCAN). On 8 MHz HSE boards its input has been 1.6 MHz (M=5) since H7 support was added. KAKUTEH7WING (16 MHz HSE, M=10) uses the same input.
That input is out of spec for the configuration in use. The datasheet (DS12110, rev Y Table 50 and rev V Table 147) gives these limits:
The code pairs a 1.6 MHz input with an 800 MHz VCO, which satisfies neither row. A PLL run out of spec can still lock but with excess jitter or marginal lock. That would be consistent with the unreliable SD card reports on H7. DroneCAN is new in 10.x, so it has little field time on this clock.
Change
The VCO stays at 800 MHz, so the P/Q/R outputs (400/80/200 MHz) do not change. Only the input divider and range change:
An unsupported HSE value now gives a clear
#error.PLL1 (CPU clock) already uses a 2 MHz input and is not touched here.
This PR is stacked on #12184 (25 MHz HSE support, same lines). Its first commit is #12184's; please merge #12184 first, or review only the second commit.
Testing
sd_info/ MSC mode, and DroneCAN node communication if available.