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Release 0.2.28 - #420

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lovyan03 merged 6 commits into
m5stack:masterfrom
ainyan03:release_0.2.28
Oct 25, 2026
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lovyan03 merged 6 commits into
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ainyan03:release_0.2.28

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Board fixes

  • CoreP4X: the IMU X axis was reversed; the accelerometer and gyroscope X axes are inverted in the board mapping. (by @hlym123, Fix CoreP4X IMU X-axis orientation #414)
  • External displays (Module Display, Unit OLED / MiniOLED / GLASS / GLASS2 / LCD, Module RCA, Unit RCA): begin() reset and cleared them regardless of cfg.clear_display; they now follow the flag like the internal display. (begin(): external displays follow cfg.clear_display #416)
  • RX8130 RTC: begin() enabled backup charging (CHGEN) on every board, so ToughC5 charged its CR2032 primary cell. Charging is now on only where VBAT holds something chargeable (Tab5, StamPLC, StopWatch, PaperMono) and is cleared on the other boards, including a bit left set by an earlier firmware. The bit is cleared only when the internal RTC is initialized (not with cfg.internal_rtc = false). Code that constructs RX8130_Class directly gets charging off by default; pass true as the fourth constructor argument for a rechargeable backup. (RX8130: do not charge the RTC backup on boards with a primary cell #418)
  • Tab5: periodic RTC timer IRQs are no longer enabled on the built-in RTC. setTimerIRQ() with a positive period stops any running timer and returns 0, and Power.timerSleep(int seconds) returns without sleeping; use timerSleep(time) or timerSleep(date, time). (Tab5: do not enable periodic RTC timer IRQs #419)
  • RX8130 RTC: begin() and disableIRQ() also stop the periodic timer (the IRQ flags are kept for getIRQstatus()), and setAlarmIRQ() clears the alarm flag before enabling the alarm interrupt. (Tab5: do not enable periodic RTC timer IRQs #419)
  • Power.timerSleep(time) / timerSleep(date, time): return without sleeping when no RTC is available or the RTC driver reports that the alarm could not be set. (Tab5: do not enable periodic RTC timer IRQs #419)

Audio

  • M5Stack Core (internal DAC): a short pop at the start and at the end of each sound. The fade-out was written in whole DAC steps (a staircase of 1-LSB clicks at the default volume), and after about 85 ms of silence I2S and the DAC were stopped, so the next sound stepped the output when they were turned on again. The hold level and the fades now carry the fraction below one DAC step, and I2S keeps running at the zero level for about one second after a sound, so pauses in a melody no longer restart it. (Speaker (internal DAC): remove the pops at the start and end of a sound #415)

Requires M5GFX 0.2.35 or later.

luoweiyuan and others added 6 commits October 25, 2026 00:09
Invert the BMI270 accelerometer and gyroscope X axes in the CoreP4X board mapping. Keep the existing Z inversion and user axis-order handling.

(cherry picked from commit e5494bf)
On the internal 8-bit DAC (M5Stack Core), two steps were audible around
every sound:

- End: the hold level and the half-cosine ramp to 0 were written as whole
  DAC steps. At the default volume the bias is only a few steps, so the ramp
  became a staircase of 1-LSB clicks. The hold level and both ramps now carry
  the fraction below one step per sample, like the playback path does. The
  ramps use a smoothstep curve in integer math instead of cosf per sample.
- Start: after about 85 ms of silence I2S was stopped and the DAC disabled;
  restarting them stepped the DAC output by about 40 mV before the next
  sound. On the DAC, I2S now keeps running at the zero level for about a
  second before it is stopped, so pauses inside a melody or between key
  clicks no longer stop it. A sound after a longer silence still steps once.
  When end() wakes the task during that second, the rising ramp of a fixed
  dac_zero_level is skipped, so the pin does not jump to the bias just
  before it is pulled low.

External I2S DACs and the buzzer output are unchanged.

(cherry picked from commit 0ecbc0c)
Module Display, Unit OLED / MiniOLED / GLASS / GLASS2 / LCD, Module RCA
and Unit RCA were initialized with init() regardless of cfg.clear_display,
so they were reset and cleared even when the sketch asked to keep the
display (m5stack/M5GFX#370). They now follow the flag like the internal
display and Unit PoE-P4: init() when it is true, init_without_reset(false)
otherwise. The default is unchanged.

(cherry picked from commit 2dc8542)
begin() set CHGEN on every board. ToughC5 has a CR2032 primary cell on VBAT with
no series resistor, so M5.begin() enabled charging of a non-rechargeable cell.

CHGEN is now a constructor option (default off), set per board in
RTC_Class::begin(): on for boards whose VBAT holds something chargeable
(Tab5: supercapacitor, StamPLC: rechargeable cell, both through 1 kOhm;
StopWatch / PaperMono: capacitor), off for ToughC5 and for boards whose backup
is unknown. begin() clears the bit explicitly, because it survives on VBAT
after an earlier firmware set it. INIEN stays on for every board (the datasheet
sets it for both cell types).
On Tab5 the interrupt output of the built-in RX8130 is connected to the
power management controller. Periodic timer IRQs are not supported there.

- The built-in RX8130 on Tab5 is created with periodic timer IRQs
  disabled. A positive period passed to setTimerIRQ(), through M5.Rtc or
  the driver, stops any running timer and returns 0. setTimerIRQ(0)
  still stops the timer.
- Power::timerSleep(int seconds) returns without sleeping on Tab5. Use
  timerSleep(time) or timerSleep(date, time) instead.

RX8130 (all boards):
- begin() stops the periodic timer. The IRQ flags are kept for
  getIRQstatus().
- disableIRQ() also stops the periodic timer and reads the registers
  back to check it.
- setAlarmIRQ() keeps the alarm interrupt disabled while the alarm
  registers are written, and clears the alarm flag before enabling it.

Power::timerSleep(time) and timerSleep(date, time) (all boards) now
return without sleeping when no RTC is available or the RTC driver
reports that the alarm could not be set.
@lovyan03
lovyan03 merged commit 368ad60 into m5stack:master Oct 25, 2026
28 checks passed
@ainyan03
ainyan03 deleted the release_0.2.28 branch October 25, 2026 02:19
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2 participants