[sensei-hacker]

Summary

SYNERDUINOH7 and SYNERDUINOH7A (HSE_MHZ 25) fail to build on maintenance-10.x: the PLL2 (SDMMC/FDCAN) setup asserts HSE_VALUE % 1600000 == 0.

This adds a 25 MHz HSE case for both PLLs. M=10 gives a 2.5 MHz VCO input, inside the 2-16 MHz input range the wide-range VCO requires (DS12110, Table 50). N is chosen so that each PLL keeps its existing VCO frequency, which leaves every P/Q/R output unchanged:

PLL	8 MHz HSE (unchanged)	25 MHz HSE (this PR)
PLL1 rev Y	M=4, N=400, VCO 800 MHz	M=10, N=320, VCO 800 MHz
PLL1 rev V	M=4, N=480, VCO 960 MHz	M=10, N=384, VCO 960 MHz
PLL2	M=5, N=500, VCO 800 MHz	M=10, N=320, VCO 800 MHz

Before this change, PLL1 used M = 25/2 = 12 with a 25 MHz HSE. That ran the core at 417 MHz on rev Y. On rev V it ran at 500 MHz with a 1000 MHz VCO, which is outside the VCO's specified range.

The #else branches are unchanged, so 8 and 16 MHz HSE targets compile to the same configuration as before.

Testing

• SYNERDUINOH7 and SYNERDUINOH7A: failed to build before this change; both build now.
• MATEKH743 (8 MHz HSE, SDIO + DroneCAN) and KAKUTEH7WING (16 MHz HSE) still build, with no warnings.
• Not yet flown or bench-tested on Synerduino hardware.

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PR Summary by Qodo

Fix STM32H7 PLL clocks for 25 MHz HSE boards

🐞 Bug fix 🕐 10-20 Minutes

AI Description

• Enable SYNERDUINOH7 and SYNERDUINOH7A builds with a 25 MHz external oscillator.
• Preserve PLL1 core and PLL2 peripheral frequencies using valid 25 MHz divider settings.
• Leave existing 8 and 16 MHz clock configurations unchanged.

Diagram

graph TD
  HSE["HSE input"] --> Check{"25 MHz?"} -->|Yes| New["25 MHz dividers"] --> PLL1["PLL1 clock"] --> Core["Core clock"]
  Check -->|No| Existing["Existing dividers"] --> PLL2["PLL2 clock"] --> Peripheral["SDMMC and FDCAN"]
  New --> PLL2
  Existing --> PLL1

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High-Level Assessment

Keep the targeted 25 MHz branches. They preserve established PLL outputs without changing the 8 and 16 MHz paths; a generalized PLL calculator or configuration table would add complexity for this single new oscillator frequency.

Files changed (1) +19 / -3

Bug fix (1) +19 / -3

system_stm32h7xx.cSelect valid PLL1 and PLL2 settings for a 25 MHz HSE +19/-3

Select valid PLL1 and PLL2 settings for a 25 MHz HSE

• Adds a 25 MHz PLL1 divider and scaled multiplier for both silicon-revision configurations, preserving their VCO and core frequencies. Sets PLL2 to a valid 2.5 MHz input and 800 MHz VCO for SDMMC and FDCAN, while retaining the previous configuration and divisibility assertion for other HSE values.

src/main/target/system_stm32h7xx.c

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Code Review by Qodo

🐞 Bugs (0) 📘 Rule violations (0) 📎 Requirement gaps (0)

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[sensei-hacker]

@synersignart can you please test?

[github-actions]

RAM / Flash usage vs. base commit bc76329 — commit 9f09c89

Target	Flash Δ	RAM Δ
MATEKF405	±0 B (±0.00%)	CCM: ±0 B (±0.00%) RAM: ±0 B (±0.00%)
MATEKF722	±0 B (±0.00%)	ITCM_RAM: ±0 B (±0.00%) RAM: ±0 B (±0.00%) TCM: ±0 B (±0.00%)
MATEKF765	±0 B (±0.00%)	DTCM_RAM: ±0 B (±0.00%) SRAM1: ±0 B (±0.00%)
MATEKH743	±0 B (±0.00%)	D2_RAM: ±0 B (±0.00%) DTCM_RAM: ±0 B (±0.00%) ITCM_RAM: ±0 B (±0.00%) RAM: ±0 B (±0.00%)

See RAM/flash optimization guide for techniques to reduce usage.

[github-actions]

Test firmware build ready — commit 9f09c89

Download firmware for PR #12184

251 targets built. Find your board's .hex file by name on that page (e.g. MATEKF405SE.hex). Files are individually downloadable — no GitHub login required.

Development build for testing only. Use Full Chip Erase when flashing.

[synersignart]

yas ok we'll check on it, thanks